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FDS_6533_6534_004
71M6533/G/H and 71M6534/H Data Sheet
The page erase sequence is:
1. Write the page address to FLSH_PGADR[5:0] ( SFR 0xB7[7:2] ).
2. Write the pattern 0x55 to FLSH_ERASE ( SFR 0x94 ).
Note: Transitions to BROWNOUT mode must be avoided during page erase operations.
Bank-Switching
The program memory of the 71M6533/71M6534 consists of a fixed lower bank of 32 KB, addressable at
0x0000 to 0x7FFF plus an upper banked area of 32 KB, addressable at 0x8000 to 0xFFFF. The upper 32
KB space is banked using the I/O RAM FL_BANK[2:0 ] register as shown in Table 38. : Note that when
FL_BANK[2:0] = 0, the upper bank is the same as the lower bank.
Table 38: Bank Switching with FL_BANK[2:0]
71M6533/H
71M6534
FL_BANK[1:0]
71M6534H
71M6533G
FL_BANK[2:0]
Address Range for Lower Bank Address Range for Upper Bank
(0x000-0x7FFF) (0x8000-0xFFFF)
00
01
10
11
Not applicable
in 71M6533/H
and 71M6534
000
001
010
011
100
101
110
111
0x0000-0x7FFF
0x0000-0x7FFF
0x8000-0xFFFF
0x10000-0x17FFF
0x18000-0x1FFFF
0x20000-0x27FFF
0x28000-0x2FFFF
0x30000-0x37FFF
0x38000-0x3FFFF
Program Security
When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE
operations are blocked. This guarantees the security of the user’s MPU and CE program code. Security
should be enabled by MPU code that is executed during the pre-boot interval (60 CKMPU cycles before
the primary boot sequence begins). Once security is enabled, the only way to disable it is to perform a
global erase of the flash, followed by a chip reset.
The first 60 cycles of the MPU boot code are called the pre-boot phase because during this phase the
ICE is inhibited. A read-only status bit, PREBOOT , identifies these cycles to the MPU. Upon completion
of pre-boot, the ICE can be enabled and is permitted to take control of the MPU.
The security enable bit, SECURE , is reset whenever the chip is reset. Hardware associated with the bit
permits only ones to be written to it. Thus, pre-boot code may set SECURE to enable the security feature
but may not reset it. Once SECURE is set, the pre-boot code is protected and no external read of program
code is possible
Specifically, when SECURE is set, the following applies:
?
?
?
The ICE is limited to bulk flash erase only.
Page zero of flash memory, the preferred location for the user’s pre-boot code, may not be
page-erased by either MPU or ICE. Page zero may only be erased with global flash erase.
Writes to page zero, whether by MPU or ICE are inhibited.
MPU/CE RAM
The 71M6533 and 71M6534 includes 4 KB of static RAM memory on-chip (XRAM) plus 256 bytes of internal
RAM in the MPU core. The 4 KB of static RAM are used for data storage for both MPU and CE operations.
Rev 2
41
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